CPU, Nanometres and How Chips Are Actually Made
A chip sold as three nanometres has nothing on it that is three nanometres across. This video explains what the number in a chip's name really is, and how chips are actually made.
It starts with the first transistor at Bell Labs (16 December 1947), Kilby's first integrated circuit (12 September 1958) and Noyce's planar chip, then Moore's 1965 prediction and Dennard's 1974 scaling paper. From the Intel 4004 (15 November 1971, 2,300 transistors, a 10-micron process) to the late 1990s, a node's name was its gate length. Then the two came apart: by Intel's own account, nanometre naming stopped matching the gate length in 1997.
Then the factory: silicon purified to eleven nines, grown into a single-crystal ingot and sliced into 300 mm wafers; lithography, where up to 100 layers are printed with light through a mask; and ASML's extreme ultraviolet machines, which make 13.5 nm light by hitting tin droplets with lasers up to 50,000 times a second.
Every figure is on screen with its source and date. Vendor performance figures are the companies' own claims, shown against the baseline node they name.
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Sources and credits
Photo credits (Wikimedia Commons)
- John Bardeen, William Shockley and Walter Brattain, inventors of the transistor, Bell Labs publicity photo 1948: AT&T; photographer: Jack St. (last part of name not stamped well enough to read), New York, New York., Public domain - https://commons.wikimedia.org/wiki/File%3ABardeen_Shockley_Brattain_1948.JPG
- Replica of the first point-contact transistor, Bell Labs, December 1947: Federal employee, Public domain - https://commons.wikimedia.org/wiki/File%3AReplica-of-first-transistor.jpg
- Bell Telephone Laboratories, Murray Hill, New Jersey, 1942 (Gottscho-Schleisner, Library of Congress): Gottscho-Schleisner Collection, Public domain - https://commons.wikimedia.org/wiki/File%3ABell_Telephone_Laboratory%2C_Murray_Hill%2C_New_Jersey._LOC_gsc.5a08489.jpg
- Intel 4004 chip layout drawing, 1971 (exhibited at VCFB 2016): Wolfgang Stief from Tittmoning, Germany, CC0 - https://commons.wikimedia.org/wiki/File%3AIntel_4004_Chip_Layout_%2829983532570%29.jpg
- Silicon crystal being grown by the Czochralski process, Raytheon plant, Newton MA, 1956: George E. Meyers, Public domain - https://commons.wikimedia.org/wiki/File%3ASilicon_grown_by_Czochralski_process_1956.jpg
- Single-crystal silicon boule (Czochralski ingot), Museum fuer Naturkunde Berlin: Sebastian Wallroth, Public domain - https://commons.wikimedia.org/wiki/File%3ASingle-crystal_silicon_boule.jpg
- Semiconductor clean room under yellow photolithography light (NASA): Uploaded by Duk 08:45, 16 Feb 2005 (UTC), Public domain - https://commons.wikimedia.org/wiki/File%3AClean_room.jpg
- ASML headquarters, Veldhoven, Netherlands, 2008: A ansems, Public domain - https://commons.wikimedia.org/wiki/File%3AASML_headquarters_Veldhoven.jpg
- TSMC factory building, Hsinchu Science Park, Taiwan, 2009: Arusanov, Public domain - https://commons.wikimedia.org/wiki/File%3ATsmc_factory_hsinchu.JPG
- Samsung Electronics Pyeongtaek semiconductor campus, 20 May 2022 (US presidential visit): Office of the President of the United States, Public domain - https://commons.wikimedia.org/wiki/File%3APresident_Biden_visited_the_Samsung_Electronics_Pyeongtaek_Campus_%281%29.jpg
Primary sources
- Computer History Museum, The Silicon Engine timeline and pages (1947 point-contact transistor; 1958 Kilby; 1959 Hoerni planar and Noyce patent; 1965 Moore; 1971 microprocessor; 1974 Dennard) - accessed 24 Sep 2026.
- Intel, 'Intel 4004 processor celebrates 40th anniversary' fact sheet, 2011 - 15 Nov 1971, 2,300 transistors, 10 micron process.
- IEEE Spectrum, Rachel Courtland, 'The Status of Moore's Law: It's Complicated', 28 Oct 2013 - Mark Bohr quote; Intel 22 nm gate 35 nm, fin 8 nm; 0.35 micron node named for its gate length in the mid-1990s.
- EEJournal, Kevin Morris, 'No More Nanometers', 23 Jul 2020 - node name against gate length; quote.
- IEEE Spectrum, Samuel K. Moore, 'A Better Way to Measure Progress in Semiconductors', 21 Jul 2020 - G48M36 for 5 nm; Paolo Gargini quote.
- Intel, 'Intel Accelerates Process and Packaging Innovations', 26 Jul 2021 (SEC 8-K exhibit 99.1) - naming stopped matching gate length in 1997; Intel 7; angstrom era.
- Intel, 'Intel Reinvents Transistors Using New 3-D Structure', 4 May 2011.
- Samsung, 'Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture', 30 Jun 2022.
- TSMC, 2nm Technology page (N2 volume production 4Q25) - accessed 24 Sep 2026.
- Intel, 'Intel Unveils Panther Lake Architecture', 9 Oct 2025 - 18A vs Intel 3 (Intel internal analysis, Feb 2024); Fab 52, Chandler, Arizona. Intel, CES 2026 release, 5 Jan 2026.
- ASML, EUV lithography systems page; 'How microchips are made'; 'Light and lasers' - accessed 24 Sep 2026.
- Reuters, 17 Dec 2025 (as republished) - only ASML has mastered EUV; about $250 million per machine; Chinese prototype in Shenzhen, chips targeted for 2028.
- Rapidus, 'What are the raw materials of semiconductors?', 27 Feb 2026 (eleven nines; Czochralski; 300 mm) and 2 nm GAA prototype release, 18 Jul 2025.
- BCG, 'Navigating the Costly Economics of Chip Making', 28 Sep 2023 - ten-year total cost of ownership $35-43bn for a fab completed in 2026.
- TSMC, 'TSMC Intends to Expand Its Investment in the United States to US$165 Billion', 4 Mar 2025.
- TrendForce, 23 Apr 2026 (TSMC roadmap), 1 Sep 2026 (Intel 14A), 22 Sep 2026 (A14 pilot, citing Commercial Times and MoneyDJ). TechSpot, 19 Dec 2025 (Exynos 2600).
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