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Semiconductor Packaging: The Hidden Bottleneck

Published · 17 min

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Every new chip announcement leads with the same number: 3 nanometres, 2 nanometres. But through 2025 and into 2026, the real constraint on how many AI chips reach the world is not transistor size at all - it is what happens after the transistors are built: semiconductor packaging.

This video explains how a bare silicon die becomes a usable chip - wire bonding, then flip-chip and ball grid array packaging - and why, as Moore's Law got harder to keep shrinking, the industry turned to 'More than Moore': packaging several chips together instead of one chip doing everything.

It explains TSMC's CoWoS (Chip-on-Wafer-on-Substrate), which stacks compute dies and high-bandwidth memory on a silicon interposer and which Nvidia's GPUs depend on; Intel's alternative, combining its EMIB bridge and Foveros 3D stacking into what Intel calls EMIB 3.5D; and the outsourced assembly-and-test (OSAT) industry - ASE, Amkor and SPIL - that has quietly packaged much of the world's chips for decades, and is now watched closely as foundries move into its territory.

It covers why AI-chip packages fail yield more often than smaller chips (warpage, and the reticle-size limit on a single interposer); why TSMC's CEO, C.C. Wei, has said CoWoS capacity is sold out through 2026, with Nvidia, Broadcom and AMD estimated to hold most of it between them and Google reportedly cutting its own TPU production target as a result; why new packaging capacity takes years to arrive even once funded; and why TSMC and Intel are now building and running more of this stage themselves, onshoring it to Arizona and New Mexico - while the actual CoWoS packaging step, for now, still happens almost entirely in Taiwan, even for wafers made at TSMC's own Phoenix, Arizona fab.

Figures reported by analysts or trade press, rather than confirmed by the companies involved, are labelled as such on screen.

Educational documentary. Not financial or investment advice.

In these topics

Chapters

  1. The wrong number everyone watches
  2. What packaging actually is
  3. Why Moore's Law needed a back door
  4. 2.5D: TSMC's CoWoS explained
  5. Intel's alternative: EMIB and Foveros
  6. The OSAT industry nobody names
  7. Why yields are failing on AI chips
  8. Sold out through 2026
  9. The three-year build-out problem
  10. Racing to own the back end
  11. Taiwan's second chokepoint
  12. What happens if this doesn't scale

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Sources and credits

Photo credits (Wikimedia Commons)

Primary sources

  • TSMC quarterly earnings-call remarks on CoWoS bookings, reported by Reuters and industry press, 2025-2026 - C.C. Wei's 'sold out through 2026' statement.
  • TrendForce, 5 August 2026 - TSMC's CoWoS capacity growth (about 70,000 wafers/month in 2025 to roughly 130,000-140,000 by end-2026) and TSMC's outsourcing of CoWoS front-end work to OSATs including ASE.
  • TrendForce, 11 August 2026 - TSMC's reported above-98% yield on its 5.5-reticle CoWoS process on selected products.
  • TrendForce, 1 December 2025 and 5 December 2025, citing South Korea's ETNews - Intel's first-ever outsourcing of EMIB packaging to Amkor's Songdo facility, and Intel's own executives on EMIB's 2nd-half-2026 ramp.
  • Intel Newsroom, 'Intel's US Advanced Packaging Enables Next-Generation AI Semiconductors', 29 July 2026 - Rio Rancho, New Mexico scaling to 8x the standard reticle limit today and over 12x by 2028.
  • Intel product documentation ('EMIB product brief') and semiwiki.com, 'Comparing Intel EMIB and Intel Foveros' - EMIB's 2017 high-volume manufacturing start, and the Data Center GPU Max's 100bn+ transistors across 47 tiles on 5 processes under EMIB 3.5D.
  • Morgan Stanley analyst research note on 2026 CoWoS capacity allocation, reported via trade press, 2025 - Nvidia ~60%, Broadcom ~15%, AMD ~11%.
  • Korea Economic Daily's report of Google's reported ~25% 2026 TPU production-target cut, repeated by other trade press, 2025-2026 - reported, not confirmed by Google.
  • TSMC press release, October 2013 - Xilinx's mass production of 28-nanometre chips on CoWoS, TSMC's first customer for the technology.
  • ECTC (Electronic Components and Technology Conference) 2023 proceedings - warpage from thermal-expansion mismatch, and yield loss past roughly 3x reticle size on a single interposer.
  • SemiWiki, 'Semiconductor Packaging History Primer'; IMAPS 2011 keynote; halbleiter.org packaging history - wire bonding and flip-chip/BGA technique and interconnect-density history.
  • Gordon E. Moore, 'Cramming More Components onto Integrated Circuits' (Electronics, 19 April 1965), via TechInsights' 'A History of Chiplets' - the 1965 root of the chiplet idea.
  • Trade-press reporting on TSMC's Phoenix, Arizona fab producing wafers (including Nvidia's Blackwell chips) since October 2025, all still packaged in Taiwan, and on Amkor's Arizona plant targeted for around 2028.
  • TrendForce-linked trade coverage, August 2026, on expected 10-20% advanced-packaging price rises and an analyst estimate of roughly 200,000 CoWoS wafers/month in 2027.

Not regulated financial advice.